Design and Implementation of Multistage Interconnection Networks for SoC Networks

摘要

In this paper the focus is on a family of Interconnection Networks (INs)known as Multistage Interconnection Networks (MINs). When it is exploited inNetwork-on-Chip (NoC) architecture designs, smaller circuit area, lower powerconsumption, less junctions and broader bandwidth can be achieved. Each MIN canbe considered as an alternative for an NoC architecture design for its simpletopology and easy scalability with low degree. This paper includes two majorcontributions. First, it compares the performance of seven prominent MINs (i.e.Omega, Butterfly, Flattened Butterfly, Flattened Baseline, Generalized Cube,Bene\v{s} and Clos networks) based on 45nm-CMOS technology and under differenttypes of Synthetic and Trace-driven workloads. Second, a network calledMeta-Flattened Network (MFN), was introduced that can decrease the blockingprobability by means of reduction the number of hops and increase theintermediate paths between stages. This is also led into significant decreasein power consumption.